This invention relates to semiconductor processing, and more particularly to critical dimension control in deep submicron lithography for fabrication of interconnects in a dual damascene process.
Devices with multilevel interconnect structures have become well known in the semiconductor industry. The dual damascene process has proven to be a successful method for building such structures. This process generally involves embedding metal lines in an interlevel dielectric (ILD) layer, and connecting metal layers by metallizing via holes formed in the ILD. In order to improve the electrical performance of the overall device, it is highly desirable that the ILD have a low dielectric constant (k less than 4). In addition, in very fine-pitch ( less than 300 nm) devices, the lines and via holes must be etched into the ILD with a critical dimension of about 100 nm. This generally requires that the etch be performed with a hardmask. Furthermore, it is often desirable for part of the hardmask to remain on the ILD, to avoid a mask removal process which might damage the ILD; this layer is sometimes called a xe2x80x9cresidual hardmaskxe2x80x9d or xe2x80x9cpermanent hardmask.xe2x80x9d Accordingly, the hardmask layer in contact with the low-k ILD should also have a low dielectric constant.
A typical hardmask for formation of lines and vias in the ILD is shown schematically in FIG. 1A. The ILD 10 is disposed on a barrier layer 1, which in turn covers the underlying level (not shown). The ILD is generally formed of a polymer such as an organic polyarylene ether thermoset dielectric, or a similar material. The hardmask includes three layers 11-13. Permanent hardmask layer 11 is formed of a low-k material (k less than 4.5); examples of such materials are organosilicates such as SiCOH (containing Si, C, O and H); SiC; SiC:H; and amorphous Si containing C and H. Layer 11 is covered by layer 12, typically silicon nitride; thicknesses of layers 11 and 12 are approximately 500 xc3x85 and 350 xc3x85 respectively. Layer 13 is typically silicon dioxide with a thickness of approximately 1500 xc3x85. The pattern for the metal lines is transferred to layer 13 (xe2x80x9cline-levelxe2x80x9d lithography), resulting in formation of exposed areas 2 in the mask, as shown in FIG. 1B. Further processing involves depositing a layer of resist 14 which is patterned to define via openings 4 (xe2x80x9cvia-levelxe2x80x9d lithography), as shown in FIG. 1C. This requires that the resist 14 be at least partially planarized over the topography introduced by patterning layer 13. Layer 13 is also subject to faceting (that is, formation of facets 3), which leads to loss of critical-dimension control. The fidelity of the pattern transfer is also degraded by roughening of the line edge, caused by deposition thereon of plasma polymers.
Furthermore, as shown in FIG. 1D, in subsequent processing the etched lines and via openings are overfilled with metal 16 (often with a liner 15); the excess metal must then be removed, typically by chemical-mechanical polishing (CMP). If the metal 16 and liner material 15 are removed by CMP at nearly the same rate (for example, when metal 16 is copper and liner 15 is tungsten), the remaining hardmask must also function as a polish stop layer. The thin layer 12 of silicon nitride may not be effective as a CMP stop layer.
There is a need for an improved dual damascene process in which the hardmask structure permits processing with very high fidelity pattern transfer while retaining the advantages of low dielectric constant, and includes an effective CMP stopping layer.
The present invention addresses the above-described need by providing a dual damascene process using a hardmask structure including a sacrificial hardmask layer and which eliminates at least the oxide layer overlying the low-k dielectric layer.
In accordance with a first aspect of the invention, a method is provided in which three hardmask layers (lower, middle and top) are deposited on a low-k substrate. The top hardmask layer has a thickness less than about 200 xc3x85. A first opening is formed in the top hardmask layer in accordance with a first pattern, thereby exposing a portion of the middle hardmask layer. A second opening is formed in that portion of the middle hardmask layer in accordance with a second pattern and a corresponding opening in the lower hardmask layer, thereby exposing a portion of the substrate. An opening is formed in the substrate, and metal is deposited therein. Excess metal may be deposited over the hardmask and then removed. Finally, the top hardmask layer is removed.
The material of the top hardmask layer may be a refractory metal, a refractory metal nitride, a refractory metal alloy or a conductive Si-based material such as doped Si or doped amorphous Si, and is preferably a refractory metal nitride such as TaN. The middle hardmask layer is preferably SiN. The excess metal may be removed by CMP, with the top hardmask layer having a lower polishing rate than the excess metal being polished.
It should be noted that the process of forming the first opening may include depositing a resist layer on the top hardmask layer and subsequently removing the resist layer therefrom; the middle hardmask layer protects the lower hardmask layer from oxidation during removal of the resist layer.
In accordance with a second aspect of the invention, a method is provided in which a lower hardmask layer and a top hardmask layer are deposited. A protective layer is formed in a region of the lower hardmask layer adjacent to the top surface thereof; this protective layer protects the lower hardmask layer from oxidation when the resist removal is performed. The protective layer may be formed by exposing the lower hardmask layer to a plasma treatment which either forms a protective nitride layer in the top surface region, or densifies the lower hardmask layer in that region. The protective layer has a thickness of approximately 100 xc3x85.
In accordance with an additional aspect of the invention, a method is provided in which a lower hardmask layer and a top hardmask layer are deposited on the substrate. A first opening is formed in the top hardmask layer in accordance with a first pattern, thereby exposing a portion of the lower hardmask layer. This process includes depositing a resist layer on the top hardmask layer and subsequently removing the resist layer therefrom; the resist layer is removed in a non-oxidizing resist strip process, so that oxidation of the lower hardmask layer is avoided. In particular, the resist may be removed in a plasma resist strip process with a reducing chemistry.
It is noteworthy that the top hardmask layer is a thin sacrificial layer which can also serve as a CMP stopping layer, and that oxidation damage to the lower hardmask layer (which generally is of a low-k material) is avoided.